Ex parte CHAPIN et al. - Page 2




          Appeal No. 95-3912                                                          
          Application 08/087,247                                                      


               Appellants have appealed to the Board from the examiner’s              
          final rejection of claims 1 to 23, which constitute all the                 
          claims in the application.                                                  
               Representative claim 1 is reproduced below:                            
               1.  A chain interface controller for controlling a                     
          plurality of integrated input/output controllers, wherein the               
          requirement for a dedicated programmed microprocessor for                   
          handling data conversion for said chain interface controller                
          is removed, said chain interface controller comprising:                     
               oversampling means for eliminating random voltage spikes               
          from an input chain of digital data, the input chain                        
          comprising a plurality of bits, each bit of said plurality of               
          bits corresponding to an integrated input/output controller                 
          and representative of a state of said corresponding integrated              
          input/output controller, said oversampling means eliminating                
          random voltage spikes on said input data chain by sampling                  
          each bit of said chain of digital data on a bit-by-bit basis                
          three times during a clock period of the chain of data, each                
          sample being taken at a first predetermined interval from an                
          immediately previous sample, said oversampling means                        
          outputting a binary value of each bit of said chain of data,                
          said binary value being representative of a majority of three               
          samples of each bit taken during the clock period, said binary              
          value being an oversampled bit of said chain of digital data;               
               filter means for debouncing said input chain of digital                
          data by receiving said oversampled bits of data from said                   
          oversampling means and filtering each of said oversampled bits              
          three times at a second predetermined interval and storing a                
          filtered sample representative of three successive non-                     
          changing samples in a filtered input register, said second                  
          predetermined interval being representative of a frame clock                
          period;                                                                     
               input data change detecting means for detecting a change               
          in any bit of the chain of data and changing a status bit of                
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