Appeal No. 95-3912
Application 08/087,247
the input data chain, said status bit indicating a change of
state of any bit of the input data chain;
interrupt signal generating means generating an interrupt
signal when one bit of the input data chain has changed state,
said interrupt signal being transmitted to a host
microprocessor, said host microprocessor locating and reading
said filtered sample upon the receipt of said interrupt
signal;
a serial output data line for transmitting said input
chain of digital data to said oversampling means from said
plurality of integrated input/output controllers; and
a serial input data line for transmitting an output chain
of digital data, said output chain of digital data being a
serialized version of parallel output data generated by said
host microprocessor for providing instructions to said
integrated input/output controllers.
The following references are relied on by the examiner:
Fisk et al. (Fisk) 4,120,034 Oct. 10,
1978
Daughton et al. (Daughton) 4,266,294 May 05,
1981
Federico et al. (Federico) 4,550,382 Oct. 29,
1985
Claims 1 to 23 stand rejected under 35 U.S.C. § 103. As
evidence of obviousness, the examiner relies upon Fisk in view
of Federico as to claims 1, 3 to 9, 11, 13, 14 and 16 to 23,
with the addition of Daughton as to claims 2, 10, 12 and 15. 2
2A rejection of one claim under the second paragraph of
35 U.S.C. § 112 is not repeated in the answer from the final
3
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