Appeal No. 95-4708
Application 08/127,782
The Rejection on Appeal
Claims 1-56 stand finally rejected under 35 U.S.C. § 103 as
being unpatentable over Hinton and Johnson (Paper No. 5, pages 2
and 4).
The Invention
The invention is directed to an apparatus and method for
storing results of an executed set of operations into a register
file. In particular, the individual operations target the same
register or the same portion of a register. Based in part on a
prioritizing scheme, the operation results are written into the
register file within one clock cycle. In that regard, however,
claim 1 recites one half clock cycle rather than one clock cycle.
The independent claims are claims 1, 10, 19, 27, 35, 43, 51
and 54. Representative claim 19 is reproduced below:
19. An apparatus for storing results of multiple executed
uops into a register file within one clock cycle, said uops
executed by a superscalar microprocessor, said register file
having a plurality of registers, said apparatus comprising:
memory logic for receiving names of a first destination
register and a second destination register, said first
destination register targeted by a first uop and said second
destination register larger than said first destination register
and targeted by a second uop;
merging logic for generating an enable signal for said
second uop that corresponds to said first destination register if
said second destination register includes said first destination
register;
2
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Last modified: November 3, 2007