Appeal No. 95-4708
Application 08/127,782
priority logic for asserting a write enable signal
corresponding to said first destination register for a highest
priority uop between said first and said second uop, if said
first and said second uop have enable signals corresponding to
said first destination register; and
enable logic for steering data associated with said highest
priority uop from said memory logic to said first destination
register of said register file according to said write enable
signal within said one clock cycle.
Opinion
We do not sustain the rejection of claims 1-56 under
35 U.S.C. § 103 as being unpatentable over Hinton and Johnson.
Each of the independent claims 1, 10, 19, 27, 35, 43, 51 and
54, in one form or other, requires the results of operations
targeting the same register, in whole, part or portion, or
corresponding enable signals, to be prioritized such that the
results are written into the commonly targeted area within one
clock cycle according to that priority. In the context of the
appellants’ disclosure, the writing of plural results into the
same targeted area in the same clock cycle according to a
determined priority does not mean that each of the results is
actually written in the same clock cycle. Rather, the writing of
that result which would become overwritten in the same clock
cycle if the operations are orderly executed is given a lower
priority and thus omitted, skipped, or ignored. See the
specification from page 15 to page 18. The end result achieved
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