Appeal No. 95-4708
Application 08/127,782
scoreboard bit that is used to mark it busy if a long
instruction. This scoreboard bit is checked during
q12.
The appellants correctly argue (Br. at 6) that Hinton’s
solution to conflicting access to the same register area is to
delay the issuance of one of the operations to eliminate the
conflict. The appellants are correct (Br. at 6) that Hinton’s
scheme "fails to allow a register file update of two or more
operations targeting the same register (or portion thereof)
within a single clock cycle as allowed by the present invention
as claimed." In other words, no writing of results is
effectively carried out by being omitted, ignored, or deleted.
Further in support of their argument, the appellants point
out (Reply at 2) that Hinton indicates (column 5, lines 45-60)
that its register file 6 is more particularly described in patent
application 07/486,407 (now Patent No. 5,185,872 to Arnold et
al.). The appellants refer (Reply at 6) to the following
description in Arnold et al. (Column 5, line 65, to column 6,
line 5):
Since the both register and memory types of
instructions allowed to execute in the same cycle, six
possible register requests could be executing. Thus, a
6-port register file design is required to correctly
implement these parallel functions. Of course, a
mechanism must exist that prevents the collision of
data, since writing the same register from multiple
sources could be disastrous. To protect against this
6
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