Appeal No. 95-4708
Application 08/127,782
at the end of the clock cycle is as if all operations targeting
the same area were performed. That is the proper interpretation.
Neither the appellants nor the examiner urges a different view.
The issues on appeal center about whether Hinton and Johnson
discloses or suggests, whether alone or in combination with each
other, the writing of results into the same targeted register
part or portion within the same clock cycle, a feature which the
examiner has not denied is required by all the independent
claims. The appellants argue that they do not. We agree.
With regard to the register file RF 6 of Hinton, the
examiner stated (answer at 3):
The register file (RF) 6 is multi-ported, including two
write ports. The RF can receive the results of two
operations simultaneously. The REG coprocessors 10 can
write the results of an arithmetic operation to the RF
6, simultaneously with the MEM coprocessors 10 loading
an operand to the RF 6 from external memory. In other
words, results of concurrently executing micro-
operations can be written to the RF 6 simultaneously.
Also, in response to the appellants’ argument, the examiner
pointed to a portion of Hinton which defines two access ports for
the register file 6 which (column 12, lines 64-66) "allow LOAD
data from a previous read operation and STORE data from a current
write access to be processed in the register simultaneously."
The problem with the examiner’s position is that Hinton
evidently is discussing simultaneous access to the register file
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