Appeal No. 95-4708
Application 08/127,782
"effectively" writing into the same targeted register areas in
the same clock cycle (one of the writing is not just delayed to
be processed at another time), not a different arbitration scheme
which puts the conflicting operations in another order.
The appellants correctly argue (Br. at 9) that Johnson does
not teach or suggest that multiple operations can update the same
destination register (or portion thereof) within a common clock
cycle. The appellants further correctly note (Br. at 9-10) that
in its section 6.1.2, Johnson teaches that results from the
reorder buffer are written into the register file "in sequential
order." The examiner has failed to demonstrate how Johnson would
reasonably suggest writing into the same register areas in the
same clock cycle.
For the foregoing reasons, neither Hinton nor Johnson
reasonably would have suggested writing into the same register
parts in the same clock cycle. We also see no reason why or how
their combination would have suggested writing into the same
register parts in the same clock cycle. Accordingly, the
rejection of claims 1-56 under 35 U.S.C. § 103 as being
unpatentable over Hinton and Johnson cannot be sustained.
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