Appeal No. 96-4033
Application No. 08/086,354
arguments presented in the appeal brief. Claims 2 and 12 have
been canceled.
The invention pertains to a data processor. Claim 11,
the only independent claim before us on appeal, is illustrative
and reads as follows:
11. A processor comprising:
means for executing a sequence of instructions of fixed length having
sequential addresses, and detecting a conditional branch instruction in said
sequence, said branch instruction having an opcode and a signed displacement;
means for detecting the sign of said displacement in said branch
instruction;
means for (a) fetching a next instruction of said sequence, said next
instruction having an address in sequence with said branch instruction, if said
detected sign of said displacement is positive, or (b), in the alternative,
fetching a branch target instruction not in said sequence, said target instruction
having an address determined by said displacement, if said detected sign of said
displacement is negative;
and means for testing a register defined in said branch instruction to
determine a condition specified by said opcode, after said means for fetching has
started fetching said next instruction or said branch target instruction.
The reference relied upon by the examiner as evidence of
obviousness is:
Lee et al. (Lee) 4,755,966 July 5, 1988
The appealed claims stand rejected as under 35 U.S.C. §
103 as being unpatentable over Lee.
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