Appeal No. 96-4033
Application No. 08/086,354
The respective positions of the examiner and the
appellant with regard to the propriety of these rejections are set
forth in the final rejection (Paper No. 22) and the examiner's
answer (Paper No. 29) and the appellants’ brief (Paper No. 28) and
reply brief (Paper No. 30).
Appellants’ Invention
The invention relates to apparatus for efficient
branching in a central processing unit. The apparatus makes use
2
of unused bits in the opcode of a computer instruction to provide
a hint of an expected target address for branch and jump
instructions. Because target address bits are stored in the
computer instruction, the target can be prefetched before the
actual address has been calculated and placed in a register. If
the target address of the hint matches the calculated address when
the instruction is actually executed, then the access of the data
2 “Opcode” is short for “operation code” and relates to the
execution of an instruction. An “operation code” is a recognized
term of art setting forth the list of operation parts in an
instruction, together with the names of the corresponding
operations.
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