Appeal No. 1997-4061
Application 08/469,498
(c) a read-only memory connected for providing to
the data bus, under control of a read-only memory address on
the address bus, an instruction held in the read-only memory
at a location designated by the read-only memory address, said
read-only memory having a plurality of locations that hold a
plurality of program instructions, said plurality of program
instructions
collectively comprising a program including a plurality of
interrupt processing routines;
(d) a processor, connected to said data bus and said
address bus, that executes the program instructions;
(e) address control means responsive to the program
instructions executed by the processor for providing to the
address bus the read-only memory addresses of said plurality
of locations holding the program instructions to be executed
by the processor;
(f) a patch information memory for holding a plural-
ity of patch instructions representing a plurality of modifi-
cations to execution of the program by the processor, said
patch informa- tion memory connected for providing to the data
bus, under control of a patch memory address on the address
bus, a patch instruction held in the patch information memory
at a location designated by the patch memory address on the
address bus;
(g) switching means including a first switching
means memory, the switching means for providing to the address
bus, under the control of first control data held in the first
switching means memory, a patch memory address of a first
plurality of patch instructions in said patch information
memory in place of a read-only memory address of instructions
of a first bug portion of the program, such that the first
plurality of patch instructions are provided to the processor
3
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007