Appeal No. 1997-4061
Application 08/469,498
whichever of said first and second control data is in the
first switching means memory. Appellants argue that claim 16
recites an "interrupt signal generating means for generating
an interrupt to said processor to cause the processor to
execute a patch processing interrupt routine." Appellants
argue that nothing is either disclosed or suggested by Clarke
or Fairchild of an interrupt signal generating means for
generating an interrupt to said processor to cause the process
to execute a patch processing routine.
We note that the Examiner has not responded to
Appellants' argument in the Examiner's answer. Upon our
review of Clarke and Fairchild, we fail to find any teaching
or suggestion of this limitation. Therefore, we will not
sustain the Examiner's rejection of claim 16 under 35 U.S.C. §
103.
In view of the foregoing, the decision of the Exam-
iner rejecting claims 13 through 15 and 17 through 20 under 35
U.S.C. § 103 is affirmed; however, the decision of the Exam-
iner rejecting claim 16 under 35 U.S.C. § 103 is reversed.
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