Ex parte YAMAMOTO et al. - Page 4




          Appeal No. 1997-4061                                                        
          Application 08/469,498                                                      



          for execution in place of the instructions of the first bug                 
          portion, whereby said first plurality of patch instructions                 
          are executed by the processor in place of the instructions of               
          the first bug portion, said switching means further including               
                         i)   a second switching means memory;                        
                         ii)  means for moving, during execution of one               
          of                                                                          
                    said plurality of interrupt processing routines by                
          the                                                                         
                    processor, the first control data into the second                 
                    switching means memory, and for thereafter storing                
                    second control data into said first switching means               
                    memory and such that, during said one of said plu-                
          rality                                                                      
                    of interrupt processing routines, the switching                   
          means                                                                       


                    provides to the address bus, under the control of                 
          said                                                                        
                    second control data held in the first switching                   
          means                                                                       
                    memory, a patch memory address of a second plurality              
          of                                                                          
                    patch instructions in said patch information memory               
          in                                                                          
                    place of a read-only memory address of instructions               
          of                                                                          
                    a second bug portion of the program, such that the                
                    second plurality of patch instructions are provided               
                    to the processor for execution in place of the                    
                    instructions of the second bug portion, whereby,                  
                    during said one of said plurality of interrupt                    
                    processing routines, said second plurality of patch               
                    instructions are executed by the processor in place               
          of        the instructions of said second bug portion; and                  

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