Appeal No. 1997-4061
Application 08/469,498
iii) means for restoring, at a termination of
execution of said one of said plurality of interrupt
processing routines by the processor, the first
control
data held in the second switching means memory into
the first switching means memory
wherein said first control data includes a first portion which
consists of the read-only memory address of the first bug
portion and a second portion which consists of the patch
memory address of the first plurality of patch instructions,
and wherein the second control data includes a first portion
which consists of the read-only memory address of the second
bug portion and a second portion which consists of the patch
memory address of the second plurality of patch instruc-
tions.
The references relied on by the Examiner are as
follows:
Fairchild et al. (Fairchild) 4,296,470 Oct. 20,
1981
Clarke 0,458,559 Nov. 27,
1991
(European Patent Application)
Claims 13 through 20 stand rejected under 35 U.S.C.
§ 103 as being unpatentable over Clarke and Fairchild.
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