Appeal No. 1997-4061
Application 08/469,498
processing routines by the processor, the first control data
into the second switching means memory." Furthermore, Appel-
lants' claim 13 recites a switching means under the control of
first control data held in the first switching means memory.
Fairchild teaches in column 8, line 66, through
column 9, line 9, that when an interrupt occurs, the contents
of IAR 24 together with paging information stored in page
latches 162 and arithmetic and logic unit (ALU) status bits of
ALU status latches 120, 122 and 124 are saved into ILR 170.
We find that the information stored into ILR 170 meets Appel-
lants' claimed language "control data" and thereby reads on
Appellants' limitations recited in claim 13.
Appellants also argue that it is not clear what
would motivate one skilled in the art to incorporate the
Fairchild link registers into the Clarke system. In particu-
lar, Appellants
point out that Fairchild discloses a pre-fetch processor and
that Clarke does not disclose a pre-fetch processor and, at
10
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