Ex parte YAMAMOTO et al. - Page 8




          Appeal No. 1997-4061                                                        
          Application 08/469,498                                                      



          Appellants' invention as set forth in claim 13 except for                   
          storing the first control data from the first switching means               
          memory into the second switching means memory and restoring                 
          means for restoring                                                         





          first control data back into the first switching means memory.              
          The Examiner relies on Fairchild for disclosing this feature.               
          In particular, on page 4 of the answer, the Examiner states                 
          that Fairchild shows that the address of an instruction ad-                 
          dress register (IAR)(24) is transferred into a storage address              
          register (SAR)(26) for the purposes of addressing the instruc-              
          tion in the main storage unit (21) to be executed.  The Exam-               
          iner further points out that when an interrupt occurs, the                  
          contents of the  IAR 24 are saved in an interrupt link regis-               
          ter (ILR)(170) and when the interrupt routine is finished, the              
          contents of ILR 170 are transferred back into the SAR.  The                 
          Examiner points to Fairchild, column 2, lines 31 through 46;                
          column 3, lines 52 through 62;  and column 8, line 66, through              

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