Appeal No. 1997-0300
Application 08/138,790
DECISION ON APPEAL
This is a decision on appeal from the final
rejection of claims 11 through 24. Claims 1 through 10 have
been canceled.
The invention, as described by Appellants on page 6
of the specification, relates to a microprocessor which has a1
write buffer located between the core of a microprocessor and
a memory. Appellants identify on pages 11 and 59 of the
specification, that the memory receives data over a 64 bit
data bus (eight bytes). On page 19 of the specification,
Appellants identify that the function of the write buffer is
to receive data from the core. This data is to be written to
memory. Appellants identify on page 21 of the specification
that the buffer entries contain the data and the physical
memory address where the data is to be stored. The buffered
information is then later written to memory when the memory is
not busy with higher priority operations. Thus, the core more
rapidly performs memory write functions. On pages 59
1The page numbers referenced throughout this opinion
correspond to those of the originally filed specification, and
not the substitute specification filed on March 22, 1995.
2
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