Ex parte GARIBAY et al. - Page 11

          Appeal No. 1997-0300                                                        
          Application 08/138,790                                                      

          to memory by merging the writes together, i.e. for a 64 bit                 
          bus, two 32 bit writes will be merged into one 64 bit write.                
          See column 1, lines 51 through 66, and column 4, lines 38                   
          through 52.  Thus, we find that these features of Ardini teach              
          that data should be grouped into one write where possible.                  
          Further, we fail to find that Ardini teaches or suggests use                
          of the buffer to make writes across memory boundaries.                      
          Rather, we find that the purpose of Ardini is to make the                   
          largest write within the memory’s boundaries.                               
                    We fail to find that Ardini provides motivation to                
          modify Shimp in the manner asserted by the Examiner.  Our                   
          reviewing court has stated that “[t]he mere fact that the                   
          prior art may be modified in the manner suggested by the                    
          Examiner does not make the modification obvious unless the                  
          prior art suggested the desirability of the modification.”  In              
          re Fritch, 972 F.2d                                                         
          1260, 1266 n.14, 23 USPQ2d 1780, 1783-84 n. 14 (Fed. Cir.                   
          1992) (citing In re Gordon, 733 F.2d 900, 902, 221 USPQ 1125,               
          1127 (Fed. Cir. 1984)).  We find that Shimp’s system makes two              
          writes to different memory addresses.  See column 7, line 58.               


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