Appeal No. 1997-3911
Application 08/368,758
memory 44 from the data bus 14 and the control bus
15 provide the write enable command and the one-bit
data input for this purpose. [Col. 6, lines 8-19).
In a second embodiment of the invention, shown in Figure 3, a
single patch memory 54 performs the functions of memories 40
and 44 of Figure 1 (col. 6, lines 20-22).
The examiner's contention that Patrick generally suggests
replacing a ROM with a "more cost effective RAM" (Final Rej.
at 6) is incorrect, as should be evident from Patrick's above-
noted description of the standard "X1" memory embodiment
(presumably not a RAM) as obtainable at "low cost" and his
description of the ROM/PROM embodiment as the "simplest
embodiment." Be that as it may, Patrick clearly teaches that
either a PROM or a RAM can be used to implement his memory 44.
However, this teaching appears to be limited to implementing
off-chip memory 44 as an off-chip PROM or an off-chip RAM,
whereas claim 14 requires an on-chip RAM. Although Patrick
discloses an on-chip RAM 18, he does not indicate that it can
be used to store the correction information stored in memory
44. Furthermore, Patrick's memory 44, even if implemented as
an on-chip RAM, would not store the type of correction
information required to satisfy claim 14. The claim, by
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