Appeal No. 1998-0049
Application 08/289,028
I10, are considered to be the "mask bits" of claim 61. The
label attached to the bits is not of patentable
significance. The circuit of Vandierendonck has a set of
status conditions that can occur in operation, e.g., a flag
condition or a keyboard input can set or reset a condition
latch 47 in input and condition logic 40 (col. 6, line 67 to
col. 7, line 4). Vandierendonck has an instruction
register 31 (figure 2) which can hold four jump instructions
(figure 5) conditional on a particular set of status
conditions selected by the "class field" bits. For example,
if the "condition" is whether the condition latch is "set"
or "reset," the class field 00 causes a jump if the
condition latch is reset and the class field 01 causes a
jump if the condition latch is set. Thus, the "class field"
bits perform the same function as Appellants' "mask bits."
The instruction register 31 is connected to the input and
condition logic circuit 40. Circuitry causes the address of
the next instruction at bits I0 to I8 to be loaded from the
instruction register 31 to the address registers 36, 37 if
the condition specified by the "class field" bits is
satisfied (col. 7, lines 4-11). Therefore, we sustain the
- 10 -
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