Appeal No. 1998-0049
Application 08/289,028
be used to condition a branch instruction (Br6). This is
true. However, under our interpretation of the "class bits"
as the "mask bits," the "class bits" do select a status
condition to condition a branch instruction. Circuitry
causes the address of the next instruction to be loaded from
the instruction register 31 to the address registers 36, 37
if the condition specified by the "class bits" is satisfied
(col. 7, lines 4-11), where the address registers are
considered the program counter. Therefore, we sustain the
rejection of claim 88.
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