Appeal No. 1998-0069
Application 08/356,946
values from a sub-circuit 30 or 36 in the IC connected to
BST cells 32 and 38 in figure 2 in an operational mode and
test signals in a test mode, which allows testing of the
interconnection by the BST method.
Claim 7 is reproduced below.
7. A method of testing an interconnection between an
output of a means which, in an operational mode
supplies a fixed logic value, and a signal input of an
electronic circuit, the method comprising: (1) setting
the means and the electronic circuit to a test mode
through predetermined signals, (2) supplying test data
to a first test connection of the means and
transferring, via the output of the means, test data to
the interconnection as an alternative to the fixed
logic value, and (3) receiving result data in the
electronic circuit via the signal input and
transferring the result data to a second test
connection of the electronic circuit for verification.
The Examiner relies on the following prior art:2
Jarwala et al. (Jarwala) 5,029,166 July
2, 1991
The Examiner also cites Sauerwald et al., U.S. Patent2
4,879,717, Sauerwald et al., U.S. Patent 4,967,142, Tokuda
et al., U.S. Patent 5,384,533, and Sullivan, U.S. Patent
5,487,074, in the list of prior art of record relied upon in
the rejection of the claims under appeal (Examiner's Answer,
page 3).
However, the references are not applied in any of the
rejections. The listing of prior art in an Examiner's Answer
should be limited to the references relied on in the
rejections on appeal. See Manual of Patent Examining
Procedure § 1208.
- 3 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007