Appeal No. 1998-0069
Application 08/356,946
values (EA8-9). Since the bits of the test vector in the
memory 70 are output, we consider the Examiner's rejection
as if it had been more accurately stated.
The portion of Jarwala at column 4 cited by the
Examiner refers to the test data output (TDO) signal
generator circuitry of figure 3 during a test mode. The TDO
generator produces the test vector TD which is supplied to
O
the circuits 12 in the boundary scan arrangement of figure 1
(col. 9, lines 59-62). The circuit of figure 3 supplies
test vectors to avoid potential conflicts during testing.
Jarwala is concerned with a controller structure for
generating test vectors for the BSCs, not with a circuit
that outputs either a fixed logic value in an operational
mode or test data in a test mode.
We speculate that the Examiner is vaguely analogizing
the multiplexer arrangement in figure 3 of Jarwala to the
multiplexers in Appellants' figures 3 and 5. While it is
true that Jarwala discloses a multiplexer that outputs
either a bit of a test vector stored in the first memory 70
having a fixed value or a bit of a generated test vector
from the ATPG 85, both bits are output in a test mode, not
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