Appeal No. 1998-0069
Application 08/356,946
containing the map controls the multiplexer during testing,
but does not appear at the output (RBr2).
We agree with Appellants that the portion of Jarwala
relied on by the Examiner deals with the test mode, not with
conventional operation. The Examiner does not refute this
fact, but merely contends that the combined teachings of the
references would have provided the motivation (EA9).
Despite this lack of explanation, we consider Jarwala for
what it would have suggested to one of ordinary skill in the
art.
The Examiner's reliance on the BSC map is erroneous.
The BSC map in the second memory 78 controls the
multiplexer 76 to determine whether it outputs the
non-conflicting test vectors from the first memory 70 or the
sequence of vectors from the automatic test pattern
generator (ATPG) 85. As noted by Appellants, the bits of
the BSC map are not actually output. Apparently in response
to Appellants' argument, the Examiner states that Jarwala
includes a first memory whose output is supplied to a
multiplexer which selectively outputs signals applied to one
of its inputs and, thus, provides means to supply stored
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