Appeal No. 1998-0069
Application 08/356,946
reason for this finding is not clear, we speculate that the
Examiner may be trying to analogize the fixed states in the
holding mode to the claimed "fixed logic value signal."
However, since the holding mode plainly occurs during the
testing mode, Shiono does not disclose or suggest outputting
a fixed logic value signal during an operational mode as
claimed.
The Examiner finds that "Jarwala teaches (col. 4,
lines 17-46) in his test apparatus comprising a memory which
stores a map of the elements (boundary scan cells) and
applies during operational mode individual bit of test
vector to the test element" (FR3-4) and that Jarwala teaches
"that (col. 4, lines 36-46) during operation, the control
gate passes an individual bit to a separate one of the test
elements" (FR4).
Appellants argue that the Examiner has misread Jarwala,
because the phrase "[d]uring operation" (col. 4, line 36) is
concerned with operation in a test mode, not the normal
operational mode of the integrated circuits (Br7; RBr2).
Appellants further argue that the output of the memory
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