Appeal No. 1998-0069
Application 08/356,946
Shiono et al. (Shiono) 5,390,191 February 14,
1995
(filed January 21,
1993)
Claims 1-17 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Shiono and Jarwala.
We refer to the Final Rejection (Paper No. 10) (pages
referred to as "FR__") and the Examiner's Answer (Paper
No. 16) (pages referred to as "EA__") for a statement of the
Examiner's position and to the Appeal Brief (Paper No. 15)
(pages referred to as "Br__") and the Reply Brief (Paper
No. 17) (pages referred to as "RBr__") for a statement of
Appellants' arguments thereagainst.
OPINION
The issue is whether the combination of Shiono and
Jarwala teaches or suggests means that supplies a fixed
logic value to an output in an operational mode and which
can be set in a test mode to supply test data to the output
as an alternative to the fixed logic value signal.
The Examiner admits that Shiono does not disclose such
a means (EA5). The Examiner finds (EA5) that Shiono
discloses at column 6, lines 57-66, a holding mode in which
states of the integrated circuit do not change. While the
- 4 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007