Appeal No. 1998-1343
Application No. 08/154,695
Appellant's invention relates to a data processor capable
of accessing data stored in a memory which has a data output
capacity smaller than the data processing capacity of the
central processing unit. Claim 6 is illustrative of the
claimed invention, and it reads as follows:
6. A data processor capable of high speed accessing,
having a central processing unit for supplying a data output
control signal and address signals, comprising:
signal generating means for generating a plurality of
storage control signals and first and second address extension
signals;
memory means for storing data and sequentially outputting
a first portion of said data in response to said address
signals and said first address extension signal and a second
portion of said data in response to said address signals and
said second address extension signals; and
a plurality of register means responsive to said data
output control signal and said storage control signals, for
receiving said data from said memory means in response to said
storage control signals and outputting said data
simultaneously in response to said data output control signal.
The prior art reference of record relied upon by the
examiner in rejecting the appealed claims is:
Diehl 5,274,786 Dec. 28, 1993
(filed Nov. 28, 1990)
Claims 6, 7, and 9 through 11 stand rejected under 35
U.S.C. § 102(e) as being anticipated by Diehl.
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