Appeal No. 1998-1343
Application No. 08/154,695
As to the data output control signal, claims 6, 7, 10,
and 11 each require that the CPU generates the signal.
Further, the register means (claims 6 and 7) or temporary
storage means (claims 10 and 11) outputs data in response to
the data output control signal. In Diehl (column 2, lines 9-
12), "OEAB enables both lower and upper transceivers 106 and
104 [which the examiner equates to the claimed register or
temporary storage means] to drive their contents onto the data
bus connecting to microprocessor 100." In other words, signal
OEAB has the function of appellant's claimed data output
control signal. OEAB, however, is generated by controller
108, not by CPU 100 (see column 2, lines 30-38). Therefore,
Diehl does not explicitly disclose the claimed limitation.
The examiner, therefore, resorts to inherency, asserting
(Supplemental Answer, page 3) that the CPU inherently
generates a data output control signal. The examiner states
(id.) that
[t]he only way controller 108 can know when an i860
read cycle occurs is by some signal (electrical).
It is impossible for the controller to know when
processor i860 has been instructed to read or write
data without receiving some indication. Even if
controller 108 were a state machine or processor
6
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