Appeal No. 1998-1343
Application No. 08/154,695
itself it would still have no way of knowing when to
perform a memory read or write.
We should note here that the examiner has provided no
extrinsic evidence to establish that the CPU necessarily
generates a data output control signal, and that it would be
so recognized by persons of ordinary skill. See Continental
Can,948 F.2d at 1268, 20 USPQ2d at 1749.
Appellant responds (Supplemental Reply Brief, page 5) to
the examiner's assertion as follows:
There is no reason that the i860 microprocessor can
not be controlled by controller 108 instead of
controller 108 being controlled by the i860
microprocessor. Accordingly, it is entirely
possible that only controller 108 knows when a read
from memory is to occur. It is also possible that
both the controller and the i860 work in sync with
the 33.33 MHZ system clock XClk, wherein a
predetermined clock cycle controls whether the i860
microprocessor is in a read or write mode (see for
example Diehl's col. 5, line 5 wherein read and
write cycles are discussed). Further, there could
be some central processing controller not shown
which controls both microprocessor 100 and
controller 108.
(The above-noted quote is virtually identical to the argument
set forth in the Reply Brief at pages 5-6). Thus, appellant
has provided several alternatives which indicate that the CPU
does not inevitably generate a data output control signal, and
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