Appeal No. 1998-1343
Application No. 08/154,695
the examiner has shown no reason why the alternatives proposed
by appellant are impossible. Further, Diehl's Figure 1
indicates that the CPU actually acts in response to signals
generated by controller 108. Accordingly, we find that
Diehl's CPU does not inherently generate a data output control
signal. Consequently, we cannot sustain the rejection of
claims 6, 7, 10, and 11.
Regarding appellant's other argument, each of claims 7,
10, and 11 recites that a signal generating means generates
address extension signals have first and second logic states
during a generating period of the data output control signal.
Appellant contends that since Diehl does not show the data
output control signal, one cannot determine whether the
address extension signals (IAddr[2]) alternately have first
and second logic states during a generating period of the data
output control signal. We agree. Therefore, we further
reverse the rejection of claims 7, 10, and 11, as Diehl lacks
the additional limitation for these claims.
As to claim 9, appellant attempts (Supplemental Reply
Brief, page 4) to group claim 9 with claims 6, 7, 10, and 11.
Appellant's only argument directed specifically to the
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