Ex parte KANEKURA - Page 2




          Appeal No. 1999-0485                                                        
          Application 08/526,781                                                      


          have been canceled.                                                         




               The invention relates to operation apparatus that can be               
          used in general-purpose microcomputers or the like, and more                
          particularly, to improvement of an operation apparatus for                  
          digital signal processing.                                                  
               Independent claim 1 is reproduced as follows:                          
               1.  An operation apparatus for carrying out an                         
          instruction specifying a combined operation of an arithmetic                
          operation and a shifting operation using digital data of n bit              
          length, comprising:                                                         
               instruction decoding means for decoding the instruction                
          into an arithmetic instruction indicative of the arithmetic                 
          operation of the instruction and a shifting instruction                     
          indicative of the shifting operation of the instruction;                    
               arithmetic operation means, coupled to said instruction                
          decoder means, for receiving said digital data, carrying out                
          one of a plurality of arithmetic and logical operations                     
          according to the arithmetic instruction in response to said                 
          digital data, and providing an operation resultant data of 2n               
          bit length over one of a plurality of outputs in which at                   
          least precision of said combined operation is guaranteed;                   
               selection means, coupled to said arithmetic operation                  
          means, for selecting the one of the plurality of outputs on                 
          which said operation resultant data is provided in accordance               
          with a selection signal provided by said instruction decoding               
          means;                                                                      


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