Appeal No. 1999-0485
Application 08/526,781
shifting operation means having 2n bit width capacity,
operatively coupled to said selection means to receive said
selected operation resultant data, for carrying out a shifting
operation in response to said selected operation resultant
data according to the shifting instruction; and
rounding processing means, coupled to receive an output
value of said shifting operation means, for rounding the
output value of said shifting operation means to n-bit length
in accordance with a rounding instruction provided by said
instruction decoding means, said rounding processing means not
rounding the output value of said shifting operation means
when the arithmetic instruction is indicative of a logical
operation and rounding the output value of said shifting
operation means when the arithmetic instruction is indicative
of an arithmetic operation,
said combined operation specified by the instruction
being performed during a single instruction execution period.
The Examiner relies on the following reference:
Toriumi et al. (Toriumi) 5,260,897 Nov.
9, 1993
Claims 1, 3, 6, 11, 13 through 16, 18 through 20, and 22
through 28 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Toriumi.
Rather than reiterate the arguments of Appellant and the
Examiner, reference is made to the briefs and the answer for 1
1 Appellant filed an appeal brief on February 19, 1998.
Appellant filed a reply brief on July 10, 1998. The Examiner
mailed an office communication on July 16, 1998 stating that
the reply brief has been considered and entered.
3
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