Appeal No. 1999-1637
Application 08/417,537
columns it is taught that various well known fabrication techniques such as doping,
implanting and diffusion as expressed in dependent claims 34 and 35 are utilized as well
as etching to form the various regions comprising the various embodiments in Wong’s
whole patent. We are unpersuaded of appellants’ position as to claim 31 that the claimed
process forms a sidewall spacer as a floating gate over the entire select gate and that
such is not done in Wong. There is no order recited in claims 31, 34 and 35 of the manner
or the timing in which the various regions are formed, contrary to the apparent position
taken by appellants as to these claims. In accordance with the examiner’s views as to
Figures 9A and 9B as well as Figure 10E, the claim 31 feature is met in that the floating
gate does appear to be formed above the formation of the select gate within the channel
region 903B/923 of the select transistor 922.
Lastly, we turn to the rejection of claims 1-3, 5, 6, 8, 18, 19, 30 and 36 as being
obvious over the combined teachings and showings of Ono in view of Sugaya. We
reverse this rejection.
Ono’s Figure 1 shows a conventional sidewall-type flash EEPROM cell with three
gates comprising two transistors for each cell, such as the cells depicted in Figure 3 of this
reference. On the other hand, Sugaya is a single transistor device for the memory cells per
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