Appeal No. 1999-1637
Application 08/417,537
or a select transistor as in Ono would be fabricated in a vertical orientation and its
placement with respect to the other elements shown, for example, in Sugaya’s Figure 1.
Thus, we are left without any clear guidance as to where the location would be of the select
gate or sidewall gate 18 from Ono’s Figure 1 in Sugaya’s vertical architectural approach in
his representative Figure 1.
In order for us to sustain the examiner’s rejection under 35 U.S.C. § 103, we would
need to resort to speculation or unfounded assumptions to supply deficiencies in the
factual basis of the rejections. In re Warner, 379 F.2d 1011, 1017, 154 USPQ 173, 178
(CCPA 1967), cert. denied, 389 U.S. 1057 (1968), reh’g denied, 390 U.S. 1000 (1968).
This we decline to do. Thus, we can only but conclude that without more evidence, the
references are not properly combinable within 35 U.S.C. § 103.
In considering the teachings and showings of Sugaya alone as applicable to
independent claims 1, 5, 18, 30 and 36 within this rejection of those claims on appeal, we
conclude that Sugaya alone does not teach or show the entirety of each of these
respective independent claims. The only gates shown in representative Figure 1 of
Sugaya are the floating gate 2 and the control gate 1. Since claim 1 recites a first vertically
disposed gate that is a floating gate, this would correspond to floating gate 2 in Sugaya’s
Figure 1. However, this floating gate does not overlie the previously recited horizontally
disposed gate electrode in claim 1 since the only other gate shown in Figure 1 of Sugaya
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