Appeal No. 1999-1637
Application 08/417,537
se where Figure 1 shows two cells connected together. In this reference there is no select
transistor and therefore no select gate comparable to the second transistor of Ono’s
Figure 1, which includes the sidewall gate or select gate 18.
From our study of the examiner’s position at pages 3-5 of the answer, the examiner
proposes to modify Ono’s prior art horizontal floating gate EEPROM memory cell
arrangement in view of the vertically structured floating gate cell in Sugaya. However, the
examiner’s explanation of this combination does not propose any manner of a structural
combination, only that it would have been obvious to fabricate Ono’s device vertically as
done in Sugaya rather than horizontally.
On the basis of the examiner’s position as well as our study of both references, we
conclude that the examiner has not established a prima facie case of obviousness within
35 U.S.C. § 103. Indeed, we have concluded that there appears to be no clear basis from
the teachings and suggestions in both references as well as the examiner’s reasoning as
to how the artisan would have modified the two transistor memory cells of Ono which is
based on a horizontal architectural approach in view of the vertical architectural approach
of Sugaya. The combination appears to us to be problematic because the examiner’s
reasoning and the references do not account for any manner in which the second transistor
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