Appeal No. 2001-2425
Application No. 09/276,474
data in a normal mode of operation are also employed, via logic, in a test mode to
emulate a plurality of linear feedback shift register (LFSR)-based segments to generate
test patterns for peripheral devices having associated parallel scan registers coupled to
the processor core of the integrated circuit.
Representative independent claim 8 is reproduced as follows:
8. An integrated circuit comprising:
a processor core including data paths for processing data in a
normal mode of operation;
a plurality of peripheral devices having associated parallel scan
registers coupled to the processor core; and
operating logic to operate the data paths of the processor core in a
test mode of operation to emulate a plurality of linear feedback shift
register (LFSR) - based segments interconnected by a network of linear
functions to generate deterministic test patterns for the peripheral devices.
The examiner relies on the following reference:
Bullinger et al. (Bullinger) 4,947,395 Aug. 07, 1990
Claims 8-28 and 35-51 stand rejected under 35 U.S.C. § 103 as unpatentable
over Bullinger.
Reference is made to the briefs, paper no. 5, [non-final rejection] and the answer
for the respective positions of appellants and the examiner.
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