Appeal No. 2001-2425
Application No. 09/276,474
connection, would enable faster loading of the scan patterns and thus, faster testing of
the devices” [Paper No. 5-page 3]. The examiner also contends that the artisan would
have been led to make such a modification because Bullinger suggests “that scan
paths such a parallel connection is useful [sic] for testing integrated logic that is
connected to parallel buses (col. 4, lines 8 et seq.)” [Paper No. 5-page 3].
Bullinger clearly is a very relevant reference to the claims at hand, disclosing, as
it does, access for testing embedded logic functions within an integrated circuit without
requiring additional I/O pins.
The distinction argued by appellants, however, is that while, in the instant claims,
normally available data paths of a processor core are operated in a test mode to
implement scan testing, Bullinger uses “special-purpose” circuitry to implement a scan
test [brief-page 7, reply brief-page 3]. Moreover, argue appellants, the LSFR disclosed
by Bullinger is directed to output data compression and has nothing whatsoever to do
with test pattern generation (reply brief-page 3). But, even assuming the LSFR is
implemented using data paths of an on-chip processor core in Bullinger, appellants
argue that Bullinger still does not suggest the claimed “data paths for processing data in
a normal mode of operation” that are operated “in a test mode of operation...to
generate deterministic test patterns,” as set forth in claim 8 (reply brief-pages 3-4).
4
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007