Appeal No. 2001-2425
Application No. 09/276,474
Appellants stress that this is made clear by the fact that the language of claim 8
requires the data paths of the processor core to operate “to emulate” LFSRs, so that
while the data paths may not necessarily operate as LFSRs when processing data in a
normal mode of operation, these data paths are used to “emulate” LFSRs in a test
mode of operation (reply brief-page 4). Appellants contrast this with Bullinger’s special-
purpose circuitry which denote an LFSR, according to the examiner. Therefore,
conclude appellants, if the circuitry is in fact an LFSR, there would be no need “to
emulate” an LFSR (reply brief-page 4).
We do not agree with appellants’ conclusion that if Bullinger’s special-purpose
circuitry is, in fact, an LFSR, then it cannot be said “to emulate” an LFSR. If an element
is, in fact, itself, then it clearly “emulates” itself, as an element acting as itself is the
epitome of emulation.
However, we do agree with appellants that the instant claims require the
processor core to include data paths for processing data in a normal mode of operation
and those same data paths are then operated, by logic, in a test mode of operation, to
emulate a plurality of LFSR-based segments...to generate deterministic test patterns for
peripheral devices.
While Bullinger does provide a scan testing which does not require additional pin
connections, Bullinger is very clear that this is provided by the use of “additional
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