Appeal No. 2001-2425
Application No. 09/276,474
OPINION
It is the examiner’s position that Bullinger shows a “core processor (column 4,
lines 32 et seq.), a plurality of peripheral devices (16), associated scan registers (40-1,
40-n), operating logic for generating test patterns emulating a LFSR (18),
interconnected by a linear network (10), and compacting responses (fig. 4)” [Paper No.
5-page 3].
While the examiner notes that Bullinger does not explicitly state that the core
processor is coupled in parallel to the scan circuits, the examiner notes that Bullinger
teaches that the processor is connected to parallel data bus 14 and parallel address
bus 12, citing columns 3-4, and that Bullinger’s testing apparatus provides one or more
controlled interfaces, which are referred to as scan paths, between the data bus and
the controlled interfaces, citing column 4, line 1 et seq. and column 5, line 35 et seq.
[see Paper No. 5-page 3].
The examiner takes “official notice of both the concept and benefits, that it is
notoriously well known in the data processing art to have a processor connected in
parallel to parallel scan registers” [Paper No. 5-page 3].
From this, the examiner concludes that the artisan would have “readily realized
that modifying the connections of a processor to multiple scan paths via a parallel
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