Appeal No. 2002-0727
Application No. 08/869,878
claims on appeal. Note In re Dance, 160 F.3d 1339, 1340 n.2, 48
USPQ2d 1635, 1636 n.2 (Fed. Cir. 1998); In re King, 801 F.2d 1324,
1325, 231 USPQ 136, 137 (Fed. Cir. 1986); In re Sernaker, 702 F.2d
989, 991, 217 USPQ 1, 3 (Fed. Cir. 1983). They read as reproduced
below.
1. In a computer system including a plurality of processors,
a main memory and a cache memory, a method for managing the cache
memory comprising the steps of:
(a) dividing said cache memory into a plurality of regions;
(b) associating each of said processors with a different one
of said regions;
(c) generating an access address to said main memory that
contains data desired by one of said processors;
(d) determining if a copy of said data resides in said cache
memory;
(e) providing access to said copy of said data residing in
said cache memory if said data resides in any region within said
cache memory; and
(f) copying said data from said main memory into the region
of said cache memory associated with said one of said processors
if a copy of said data does not reside in any region within said
cache memory.
6. An apparatus for accelerating the access speed of a main
memory, comprising:
(a) a cache memory including a plurality of regions, said
cache memory is shared by a plurality of processors, each of said
processors is associated with one of said regions;
(b) means for generating an address access that contains data
desired by one of said processors; and
2
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