Appeal No. 2002-0727 Application No. 08/869,878 with the instantly claimed cache regions accessible for the claimed read operation, but inaccessible for a write operation. Furthermore, combining the separate caches of Pierce into Brenza would appear to defeat the stated goal of the partitioned cache of Brenza being able to operate independently and in parallel.1 (column 7, lines 46-48). Furthermore, we observe that the shared memory of Pierce is utilized “as a source for processor instructions and a source/destination for processed information” (column 5, lines 42- 43). It does not appear to have a local cache function. Therefore, even were there sufficient motivation to arrive at the combination, we do not see how the claimed invention would result. The separate caches for each processor are not mutually accessible to each processor, even if the shared memory might be. Both claims 1 and 6 require that access to data must be provided if the copy of the desired data resides in any region within the cache memory. In the absence of this element from the combination, we find a prima facie case of obviousness has not been made out. Consequently, we are constrained to reverse this rejection. 1 Indeed, this would appear to invite the problem of snoop, which Pierce is 7Page: Previous 1 2 3 4 5 6 7 8 9 NextLast modified: November 3, 2007