Appeal No. 2002-0727
Application No. 08/869,878
The appellant, on the other hand, urges that Pierce does not
teach a partitioned cache memory as stated by the examiner.
Rather, it is said to teach a separate local cache memory
associated with each processor, and a common memory shared by all
processors but having partitions accessible only by certain
processors. (Appeal Brief, page 6, lines 8-17). The local cache
memories are not partitioned, and each cache memory is accessible
only to its respective processor (Id., page 6, lines 18-20).
After a thorough review of Brenza and Pierce, we find
ourselves in agreement with the appellant that a prima facie case
of obviousness has not been established by the examiner.
While we agree with the examiner that Brenza teaches a
partitioned cache memory (figure 2, reference numeral 50), we note
that access to that partitioned cache is controlled by address
switches 58 and 52. Each partition operates independently and in
parallel, and may execute a store or fetch operation on each
machine cycle (column 3, lines 51-53). The partitions are
designed around the number of set-associative bins in the computer
design (column 3, lines 59-61) and ideally the number of
partitions will equal the number of data ports (column 8, lines
22-29). A partition look aside table (PLAT) identifies the
partition in which data is located and sends data requests to that
partition (column 7, lines 13-18). This enables the cache to
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