Appeal No. 2002-0727
Application No. 08/869,878
of data to its respectively assigned region. (Appeal Brief, page
3, lines 1-9). Further details of the claimed invention are as
found in claims 1 and 6 reproduced above.
The Rejection of Claims 1-10 Under 35 U.S.C. § 103 (a)
The examiner has found that Brenza discloses a computer
system having a plurality of processors, a main memory, and a
cache memory, wherein the cache memory is managed by partitioning
(Examiner’s Answer, page 4, lines 16-21). The examiner has
further found that Brenza discloses determining if a copy of
desired data resides in the cache memory; providing access if it
does; copying the data from the main memory to the cache memory if
it does not. (Examiner’s Answer, page 4, line 21 - page 5,
line 7).
The examiner has additionally found that Pierce discloses
cache control wherein snoop cycles can be inhibited by controlling
processor access to memory locations. (Examiner’s Answer, page 5,
lines 13-20).
The examiner thus concludes that it would have been obvious
to use Pierce’s association of each processor with a specific
cache memory in order to improve system efficiency (Examiner’s
Answer, page 6, lines 7-18).
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