Appeal No. 2002-0727
Application No. 08/869,878
execute a combination of stores and fetches independently and in
parallel (column 7, lines 46-57) and provides fault tolerance in
the event of chip failure (column 17, line 51 – column 18, line
27).
We do not see any disclosure of assigning partitions to
unique processors for storage operations, although there is a
discussion at column 17 relating to read-only data storage.
Pierce teaches providing each of a plurality of processors
with its own local cache (column 5, lines 35-47). The processors
share a common memory which has portions assigned to each of the
processors (column 5, lines 53-57). This is said to enhance data
integrity and reduce the so-called snoop operation which checks to
make sure processors do not maintain separate local caches of the
same information which may have been separately manipulated.
(column 5, lines 60-61).
However, we fail to see (1) why one of ordinary skill in the
art would replace the shared cache of Brenza with the separate
caches of Pierce, and (2) even were one so motivated, how the
combination of Brenza and Pierce would yield the claimed subject
matter.
As to the first point, Pierce teaches using completely
separate caches for each processor and assigned common memory
portions to reduce the snooping operation, which is inconsistent
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