Appeal No. 2003-2137
Application No. 09/236,183
level, and final removal of the passivation and sacrificial metal
layers after testing (Brief, pages 2-3).1
According to appellants, all of the claims stand or fall
together (Brief, page 4). Accordingly, pursuant to the provisions
of 37 CFR § 1.192(c)(7)(2000), we select claim 4 from the grouping
of claims and decide the ground of rejection in this appeal on the
basis of this claim alone. Representative independent claim 4 is
reproduced below:2
4. A method of [sic, testing] integrated circuit chips,
comprising the steps of:
forming an insulating layer over an integrated circuit chip;
selectively opening at least one area over existing vias;
forming a test circuit in kerf areas adjacent to the chip
prior to separating the chip from other chips formed on a
semiconductor wafer;
depositing a sacrificial metal layer over the insulating
layer and filling the at least one selectively opened area, the
sacrificial layer in direct contact with the integrated circuit
chip;
patterning the deposited sacrificial metal layer to form at
least one direct connection between the test circuit and an exposed
via;
1We refer to the Brief filed June 3, 2002, Paper No. 14, as
reinstated by the Request dated Dec. 10, 2002, Paper No. 17.
2We note that the copy of claim 4 from the Appendix to
appellants’ Brief is incorrect.
2
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