Appeal No. 2003-2137
Application No. 09/236,183
the kerf areas to separate the chip and remove the test circuits
(id.).
The examiner applies Beckenbaugh for its teaching of a chip
testing method which includes forming test circuitry in the kerf
area, forming an insulating layer 110 over the integrated circuit
chip, patterning a sacrificial metal layer 120/130 in direct
contact with the integrated circuit chip via bonding pad 78,
forming at least one direct connection between the test circuit and
an exposed via, scribing the wafer in the kerf areas to separate
the chip, and removing the test circuits and insulating layer
(Answer, pages 3-4). From these findings, the examiner concludes
that it would have been obvious to one of ordinary skill in the art
“to provide the test circuitry specifically in the kerf areas and
pattern the sacrificial metal layer as taught by Beckenbaugh et al.
in practicing the testing process of Ahmad et al.” Answer, page 4.
In our review of the examiner’s obviousness analysis, we must
first correctly construe the claim to define the scope and meaning
of each contested limitation. See Gechter v. Davidson, 116 F.3d
1454, 1457, 1460 n.3, 43 USPQ2d 1030, 1032, 1035 n.3 (Fed. Cir.
1997). During examination proceedings, claims are given
their broadest reasonable interpretation consistent with the
specification. See In re Graves, 69 F.3d 1147, 1152, 36 USPQ2d
4
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