Appeal No. 2003-1310
Application No. 09/761,738
expansion or reduction of the production scale. Recent
development of the semiconductor manufacturing techniques allows
integrating larger number of circuit elements into a single
semiconductor chip, trailed by combining various circuit
components, also known as “micro cell” or “Intellectual Property
(IP).” Each IP is composed of a plurality of circuit elements
and performs a certain function (specification, page 2, line 22
through page 3, line 2). A mask pattern of each IP is generated
and transferred to a predetermined position of the semiconductor
chip based on an overall layout information (specification,
page 34). As depicted in Figure 39, superposition marks 132 are
patterned around an IP mask pattern 131 on a mask 130, which are
used to properly position each of the IP patterns 131
(specification, page 35).
Representative independent claim 21 is reproduced as
follows:
21. A method of manufacturing a semiconductor device
for building a circuit composed of combined plural
intellectual properties into a semiconductor chip,
comprising:
arranging each mask pattern of said plural intellectual
properties for a layout pattern.
The Examiner relies on the following prior art reference:
Krolikowsky et al. (Krolikowsky) 3,760,384 Sep. 18, 1973
2
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