Appeal No. 2003-1310
Application No. 09/761,738
their layout pattern (col. 11, lines 29-46). Therefore, we do
not agree with Appellant (brief, page 6) that Krolikowsky’s mask
patterns relate to portions of a discrete component (i.e., the
FET) and do not provide mask patterns of a plurality of
intellectual properties. In that regard, as a plurality of
circuit elements are required to form an intellectual property,
the source/drain regions, the gate and the metallization of
different components of a memory array may be reasonably
considered as the circuit elements that are formed using
different mask patterns and are arranged according to a layout
pattern. Thus, the Examiner has properly corresponded the mask
patterns of the memory array as the claimed mask patterns of an
intellectual property which is formed of different elements of
the transistors, contacts and the conducting connections in the
memory array according to its specific layout. In fact, similar
to Appellant’s method of arranging the mask patterns, Krolikowsky
uses alignment marks to arrange the mask patterns of different
circuit elements to form the entire layout pattern corresponding
to that of a memory array.
In view of the analysis above, we find that the examiner has
met the burden of providing a prima facie case of anticipation as
Krolikowsky teaches a plurality of circuit elements or components
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