Appeal No. 2003-1310
Application No. 09/761,738
With regard to the rejection of the claims under 35 U.S.C.
§ 102, Appellant argues that Krolikowsky discloses a method of
fabricating a field effect transistor (FET) memory chip by using
separate masks to define and form different regions of the FET
(brief, page 6 and reply brief, page 4). Appellant further
asserts that these masks are mask patterns of a discrete
electronic component and not that of a plurality of intellectual
properties that may be arranged for a layout pattern (brief, page
6 and reply brief, page 5).
The Examiner responds to Appellant’s arguments by stating
that claim 21 merely requires arranging mask patterns of a
plurality of functional circuits where each includes a plurality
of circuit elements (answer, page 5). Relying on the breadth of
claim 21, the Examiner asserts that Krolikowsky’s method of
fabricating a field effect transistor discloses and reads on the
claimed method of arranging mask patterns (id.). The Examiner
argues that the transistor is fabricated by using mask patterns
prepared for plural circuit elements such as a gate electrode,
source and drain performing certain functions (id.).
As a general principle, a rejection for anticipation under
section 102 requires that each and every limitation of the
claimed invention be disclosed in a single prior art reference.
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