Appeal No. 2004-0550
Application No. 09/802,201
capacitor is formed on a n-type silicon region of a single
crystalline silicon substrate, with a gate dielectric formed on
the n-type region, a control gate formed on the gate dielectric
layer, n+ type source and drain regions formed along laterally
opposite sidewalls of the control gate, shallow n-type tip
implants located adjacent to the source and drain regions,
whereby the capacitor uses an electron accumulation layer beyond
one side of the gate dielectric as one surface of the capacitor
and a p-type polysilicon gate on the opposite side of the oxide
layer as the other capacitor electrode (Brief, pages 3-4).
Appellants assert that because of the positive bias on the p-type
gate, this capacitor can provide more capacitance and does not
suffer from extra polysilicon depletion as in existing devices
(Brief, page 4).
Appellants state that the claims stand or fall together,
with claim 1 as representative of the entire group (Brief,
page 5). Accordingly, we select claim 1 from the group of
claims and decide the grounds of rejection in this appeal on
the basis of this claim alone. See 37 CFR § 1.192(c)(7)(2000)
and In re McDaniel, 293 F.3d 1379, 1383, 63 USPQ2d 1462, 1465
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