Appeal No. 2004-0550
Application No. 09/802,201
(Fed. Cir. 2002). We limit our discussion to claim 1 on appeal
and to any other claims to the extent they have been separately
argued by appellants. Representative independent claim 1 is
reproduced below:
1. A method of forming a capacitor on a substrate
having circuitry comprising:
forming a pair of shallow n-type tip implants in
an n-type silicon region;
forming an n-type drain region in said n-type
silicon region;
forming an n-type source region in said n-type
silicon region;
forming a dielectric layer on said n-type silicon
region;
forming a p+ type polysilicon gate on said
dielectric layer, wherein said polysilicon gate is
doped p+ type rather than n-type of said n-type drain
and source regions; and
configuring said capacitor as a supply decoupling
capacitor to sink and source current by coupling said
polysilicon gate to a positive supply rail and by
coupling said source and drain regions to a ground
potential.
The examiner relies upon the following references as
evidence of obviousness:
3
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